1. Field of the Invention
Embodiments of the present invention generally relate to synthesized frequency generators, and more specifically to mitigating fractional spurs in fractional-N frequency synthesizer systems.
2. Description of the Related Art
Many conventional electronic systems require a plurality of signal sources, each with specific frequency characteristics. In certain systems, at least one signal source may need to generate arbitrary frequencies, with a requirement of high precision and spectral purity within a specified range. For example, to satisfy certain technical and regulatory requirements, many radio-frequency (RF) transmission systems require very precise frequency control and very high spectral purity in signal sources used in the transmission of RF signals.
A fractional-N frequency synthesizer is one common form of signal generator that may be configured to generate arbitrary frequencies within a specified range. FIG. 1 is a block diagram of a typically fractional-N frequency synthesizer 100. The fractional-N frequency synthesizer 100 typically incorporates a variable frequency oscillator, such as a voltage-controlled oscillator (VCO) 116, and control circuitry configured to form a closed-loop feedback control system for controlling the frequency of the variable frequency oscillator. The control circuitry conventionally includes a phase-frequency detector (PFD) 110, a charge pump 112, a loop filter 114, a feedback divider 120, and a sigma-delta modulator 122. The PFD 110 continuously generates an error signal that is proportional to detected phase error between two input signals such as a reference clock 130 and a feedback clock 132. The charge pump 112 operates on the error signal to generate error pulses, which are transmitted to the loop filter 114. The loop filter 114 integrates the error pulses over time to generate a filtered control voltage. The VCO 116 operates in response to the control voltage to generate an oscillating output signal with a frequency that is a function of the control voltage. The VCO output signal 134 is transmitted to the feedback divider 120, which generates the feedback clock 132. The feedback clock 132 is transmitted to one input of the PFD 110 for comparison with the reference clock 130, which is coupled to the second input of the PFD 110. Using this architecture, the VCO 116 may be controlled in a closed-loop regime to generate an arbitrary multiple of the reference clock 130.
The sigma-delta modulator 122 controls the feedback divider 120, which may be implemented with a programmable integer divider. Some programmable integer dividers are implemented with a dual-modulus prescaler. In one embodiment, the dual-modulus prescaler implements a divide by “N/N+1” scheme, such as a divide 8/9 (either divide by 8 or by 9 in any given full countdown cycle). The programmable integer divider may, for example, implement an 8-bit programmable divider. The feedback clock 132 generated by the feedback divider 120 may be, on average, equal to the frequency of the VCO output signal 134 divided by a fixed-point number that includes both an integer and a fraction component. As is well known in the art, the feedback divider 120 achieves fixed-point, or “fractional,” frequency division by dithering count values used to control the feedback divider 120. The sigma-delta modulator 122 accumulates clock cycles against the fraction component of the fixed-point number to generate a signed dither value that is added to the integer component for the next count cycle in the feedback divider 120. The signed dither value accounts for short-term accumulated error between the actual frequency of the feedback clock 132 and a target frequency of the feedback clock 132. The feedback clock 132 is compared against the reference clock by the PFD 110, which generates a negative-feedback control signal used within the control circuit to lock the VCO 116 to a frequency corresponding to the reference clock 130 frequency multiplied by the fixed-point number.
Changes in the signed dither value typically produce a slight short-term shift in the frequency of the VCO output signal 134. This type of shift or modulation of the frequency of the VCO output signal 134 may produce spectral noise in the VCO output signal 134. For example, when the signed dither value changes periodically over a period that is relatively smaller than an observation period, the VCO output signal 134 may include a fractional reference noise “spurs”. In certain scenarios, such as when the fraction component can divide evenly into the reference clock frequency 130, “fractional spurs” are generated in the VCO output signal 134. In other instances, fractional spurs may be caused by initial conditions of accumulators within the sigma delta modulator. While fractional-N frequency synthesizer circuits are well known to be very suitable for many applications, including RF systems, fractional spurs are extremely undesirable in these same applications because of high spectral purity requirements.
As the foregoing illustrates, what is needed in the art is a technique for mitigating fractional spurs in fractional-N frequency synthesizer systems.